Porous two-wafer battery

ABSTRACT

A porous two-wafer battery comprises a first wafer and a second wafer. Each of the first wafer and the second wafer comprises a substrate, a conductive layer, and a passivation layer. The first wafer is parallel to the second wafer. The passivation layer of the first wafer is closer to the passivation layer of the second wafer. The first wafer serves as an anode and the second wafer serves as a cathode. The substrate comprises a plurality of pores and a P+ doped region. The plurality of pores are symmetric with respect to a respective center of each of the first wafer and the second wafer. An adhesion promotion layer is between the conductive layer and a respective side wall of the plurality of pores.

CROSS-REFERENCE TO RELATED APPLICATIONS

This patent application claims benefit of provisional patentapplications 62/930,016, 62/930,018, 62/930,019, 62/930,020, and62/930,021 because of a common inventor, Slobodan Petrovic. Thedisclosures made in the provisional patent applications 62/930,016,62/930,018, 62/930,019, 62/930,020, and 62/930,021 are herebyincorporated by reference.

FIELD OF THE INVENTION

This invention relates generally to a porous two-wafer battery. Moreparticularly, the present invention relates to a porous silicontwo-wafer, lithium battery.

BACKGROUND OF THE INVENTION

For lithium batteries, lithium metal dendritic growth is one of the mostserious problems affecting the safety and functionality of lithium-basedbatteries. Dendrites are fractal deposits of various shapes such asneedle-like, snowflake-like, tree-like, bush-like, moss-like, andwhisker- like structures. During charging in Li metal (and Li-ion)anodes, lithium does not form a flat, homogeneous layer on the anode,but instead dendrites that can be needle-like or branched. Factorsaffecting Li dendrite growth at the anode are current density,electrolyte composition and concentration, andsolid-electrolyte-interphase layer (SEI). Dendrites grow in a non-linearfashion and in apparently random motion of the tips of the lithium. Thedendrites growth are not dominated by the direction of the electricfield. In a configuration with two planar-type electrodes, the lithiumdendrites inevitably grow towards the other electrode, penetratingthereby through the separator and causing short upon reaching theconductive surface of the opposite electrode.

Methods using polymers, block copolymers, ionomers, HF, metal ions witha higher reduction potential than Li such as Sn4+, Sn2+, Al3+, In3+,Ga3+ and Bi3+, oligomers, ionic liquids to possibly suppress thedendrites growth are reported in the battery industry. Other methodsinclude use of solid electrolyte, ceramic electrolyte, and self-healingelectrostatic shield, e.g., Cs+.

Variations of the formulations of electrolyte have also been reported.It includes modifications of the electrolyte salts: LiClO4, LiPF6,LiAsF4 and LiBF4, addition of ethers (DME and DEE), esters (PC, EC, DMCand DEC), EC/DMC and PC/DMC mixture with LiTFSI demonstrated to promotedelayed dendrite formation.

The methods above may suppress dendrite growth. But, it also introduceadditional problems such as increased side reaction and modified cyclingcharacteristics.

The growth of lithium dendrite may result in electrical short. It canlead to battery heating up, catching fire, or exploding.

Therefore, it is required for suppressing the growth of lithium dendriteespecially for a high-power density, high current, low cost battery. Itis possible to completely eliminate dendrite growth by placing thereaction of lithium reduction away from the surface of electrode andinside the pore of porous silicon. It is also possible to provide astructure that allows for high-power density and high current abilities.

SUMMARY OF THE INVENTION

A porous two-wafer battery comprises a first wafer and a second wafer.Each of the first wafer and the second wafer comprises a substrate, aconductive layer, and a passivation layer. The first wafer is parallelto the second wafer. The passivation layer of the first wafer is closerto the passivation layer of the second wafer. The first wafer serves asan anode and the second wafer serves as a cathode.

The substrate comprises a plurality of pores and a P+ doped region. Theplurality of pores are symmetric with respect to a respective center ofeach of the first wafer and the second wafer. An adhesion promotionlayer is between the conductive layer and a respective side wall of theplurality of pores.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a side view of a porous two-wafer battery in examples of thepresent disclosure.

FIG. 2 is a front view of a wafer of a porous two-wafer battery inexamples of the present disclosure.

FIG. 3 is a side view of another porous two-wafer battery in examples ofthe present disclosure.

FIG. 4 is a cross-sectional plot along AA′ of the wafer of FIG. 2 inexamples of the present disclosure.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1 is a side view of a porous two-wafer battery 100 in examples ofthe present disclosure. The porous two-wafer battery 100 comprises afirst wafer 120, a second wafer 160, and an optional electrolyteseparator 110 (shown in dashed lines) between a front side 131 of thefirst wafer 120 and a front side 171 of the second wafer 160. FIG. 2 isa front view of the first wafer 120 of the porous two-wafer battery 100in examples of the present disclosure. The first wafer 120 comprises afirst substrate 122. The first substrate 122 comprises a plurality ofpores 140 (shown in dashed lines because of the side view). The secondwafer 160 comprises a second substrate 162. The second substrate 162comprises a plurality of pores 180 (shown in dashed lines because of theside view).

In one example, the plurality of pores 140 and the plurality of pores180 are of rectangular shapes. In another example, the plurality ofpores 140 and the plurality of pores 180 are of square shapes. In stillanother example, the plurality of pores 140 and the plurality of pores180 are of circular shapes. A diameter of the plurality of pores 140 andthe plurality of pores 180 is in a range from 1 micron to 100 microns.In examples of the present disclosure, a diameter and a pitch of theplurality of pores 140 and the plurality of pores 180 is 20 microns and22 microns respectively.

In one example, a diameter of the first wafer 120 is 4 inches. Inanother example, a diameter of the first wafer 120 is 6 inches. In stillanother example, a diameter of the first wafer 120 is 8 inches. In yetanother example, a diameter of the first wafer 120 is 12 inches. Thecapacity (charge) of the first wafer 120 is 60 Ah. In yet still anotherexample, a diameter of the first wafer 120 is 18 inches. In examples ofthe present disclosure, the capacity (charge) of the first wafer 120 isin a range from 1 Ah to 100 Ah. A thickness of the first wafer is in arange from 100 microns to 750 microns.

In examples of the present disclosure, the first wafer 120 is parallelto the second wafer 160. The front side 131 of the first wafer 120 iscloser to the front side 171 of the second wafer 160 than a back side173 of the second wafer 160. The front side 171 of the second wafer 160is closer to the front side 131 of the first wafer 120 than a back side133 of the first wafer 120.

In examples of the present disclosure, the first substrate 122 of thefirst wafer 120 is made of a silicon material. The second substrate 162of the second wafer 160 is made of the silicon material.

In examples of the present disclosure, the first plurality of pores 140are symmetric with respect to a center 231 of the first wafer 120. Thesecond plurality of pores 180 are symmetric with respect to a center ofthe second wafer 160. The first plurality of pores 140 are symmetricwith respect to X-axis. The first plurality of pores 140 are symmetricwith respect to Y-axis. The second plurality of pores 180 are symmetricwith respect to X-axis. The second plurality of pores 180 are symmetricwith respect to Y-axis.

In examples of the present disclosure, a centerline 130 of the firstwafer 120 is aligned with a centerline 170 of the second wafer 160. Theporous two-wafer battery 100 may include hundreds or thousands ofcathode or anode pores.

In examples of the present disclosure, the first wafer 120 serves as ananode and the second wafer 160 serves as a cathode.

FIG. 3 is a side view of a porous two-wafer battery 300 in examples ofthe present disclosure. The porous two-wafer battery 300 comprises afirst wafer 320 and a second wafer 360. The first wafer 320 comprises afirst substrate 322 and a first passivation layer 345 on a front side331 of the first wafer 320. The first substrate 322 comprises a firstplurality of pores 340 (shown in dashed lines because of the side view).The second wafer 360 comprises a second substrate 362 and a secondpassivation layer 385 on a front side 371 of the second wafer 360. Thesecond substrate 362 comprises a second plurality of pores 380 (shown indashed lines because of the side view).

In examples of the present disclosure, the first passivation layer 345and the second passivation layer 385 are made of a material selectedfrom the group consisting of Ta2O5, HfO2, and SiN. A thickness of eachof the first passivation layer 345 and the second passivation layer 385is in a range from 30 microns to 100 microns.

In examples of the present disclosure, the first wafer 320 is parallelto the second wafer 360. In examples of the present disclosure, thefirst substrate 322 of the first wafer 320 is made of a siliconmaterial. The second substrate 362 of the second wafer 360 is made ofthe silicon material.

In examples of the present disclosure, the first plurality of pores 340are symmetric with respect to a center of the first wafer 320. Thesecond plurality of pores 380 are symmetric with respect to a center ofthe second wafer 360.

In examples of the present disclosure, the first passivation layer 345directly contacts the second passivation layer 385. A centerline 330 ofthe first wafer 320 offsets from a centerline 370 of the second wafer360 by a pre-determined distance 351. In examples of the presentdisclosure, the pre-determined distance 351 is in a range from 10% of awidth 353 of a selected pore of the first plurality of pores 340 to 50%of the width 353 of the selected pore of the first plurality of pores340.

In examples of the present disclosure, the first wafer 320 serves as ananode and the second wafer 360 serves as a cathode.

FIG. 4 is a cross-sectional plot along AA′ of the first wafer 120 ofFIG. 2 in examples of the present disclosure. The second wafer 160 hassimilar structure as the first wafer 120. The first wafer 120 comprisesa first substrate 122, a first conductive layer 430 on a respective sidewall 442 of each of the first plurality of pores 140, and a firstpassivation layer 476 on a front side of the first wafer 120. The firstsubstrate 122 comprises a plurality of pores 140 and a P+ doped region123.

The first conductive layer 430 provides electrical conductivity andserves as a reactive surface for battery reactions. The siliconsubstrate may not in contact with lithium. The first passivation layer476 prevents lithium reduction and prevents dendrite growth.

In examples of the present disclosure, the first passivation layer 476comprises a first plurality of passivation sections 477. Each of thefirst plurality of passivation sections 477 is of a first letter Ushape. A first leg 471 of the first letter U shape is directly attachedto the first conductive layer 430 of a first selected pore 491 of thefirst plurality of pores 140. A second leg 472 of the first letter Ushape is directly attached to the first conductive layer 430 of a secondselected pore 492 of the first plurality of pores 140. A length of thefirst leg 471 and a length of the second leg 472 is in a range from 20microns to 50 microns.

In examples of the present disclosure, the first conductive layer 430 ismade of a material selected from the group consisting of titaniumnitride, silicates, silicon carbide, copper, and nickel. The firstpassivation layer 476 is made of a material selected from the groupconsisting of Ta2O5, HfO2, and SiN. The first conductive layer 430 maybe formed by impregnation or deposition.

An entirety of the first conductive layer 430 is in the inner portion ofthe first plurality of pores 140. There is no direct path for electricalshort. In addition, there is no SEI layer that would initiate thedendrite growth. Furthermore, there are no edge effects of protrusion.

In examples of the present disclosure, a first adhesion promotion layer447 is between the first conductive layer 430 and the respective sidewall 442 of each of the first plurality of pores 140.

In one example, a thickness of the first conductive layer 430 is in arange from 30 microns to 200 microns. In another example, a thickness ofthe first conductive layer 430 is in a range from 100 microns to 150microns. In one example, a thickness of the adhesion promotion layer 447is in a range from 20 microns to 200 microns.

In examples of the present disclosure, each of a porous silicon anodeand a porous silicon cathode comprises 20 μm pore dimension, 22 μmpitch, 350 μm electrode thickness; TiN coating (100 μm), Ta2O5dielectric coating on the inner surface (50 μm). The cathode material isLiCoO₂ or LiMn₂O₄. The electrolyte is 1 M LiFP6 in CE/DE.

In examples of the present disclosure, the battery is held in apouch-type cell including rigid or semi-rigid containers. Anotherconductive layer may be added on top of the first conductive layer 430to further improve conductivity.

Those of ordinary skill in the art may recognize that modifications ofthe embodiments disclosed herein are possible. For example, a number ofthe first plurality of pores may vary. Other modifications may occur tothose of ordinary skill in this art, and all such modifications aredeemed to fall within the purview of the present invention, as definedby the claims.

1. A porous two-wafer battery comprising a first wafer comprising afirst substrate comprising a first plurality of pores; a firstconductive layer on a respective side wall of each of the firstplurality of pores; and a first passivation layer on a front side of thefirst wafer; and a second wafer comprising a second substrate comprisinga second plurality of pores; a second conductive layer on a respectiveside wall of each of the second plurality of pores; and a secondpassivation layer on a front side of the second wafer; wherein the firstwafer is parallel to the second wafer; wherein the front side of thefirst wafer is closer to the front side of the second wafer than a backside of the second wafer; and wherein the front side of the second waferis closer to the front side of the first wafer than a back side of thefirst wafer.
 2. The porous two-wafer battery of claim 1, wherein thefirst substrate of the first wafer is made of a silicon material; andwherein the second substrate of the second wafer is made of the siliconmaterial.
 3. The porous two-wafer battery of claim 1, wherein anelectrolyte separator is between the front side of the first wafer andthe front side of the second wafer.
 4. The porous two-wafer battery ofclaim 1, wherein the first passivation layer comprises a first pluralityof passivation sections; wherein each of the first plurality ofpassivation sections is of a first letter U shape; wherein the secondpassivation layer comprises a second plurality of passivation sections;and wherein each of the second plurality of passivation sections is of asecond letter U shape.
 5. The porous two-wafer battery of claim 4,wherein a first leg of the first letter U shape is directly attached tothe first conductive layer of a first selected pore of the firstplurality of pores; wherein a second leg of the first letter U shape isdirectly attached to the first conductive layer of a second selectedpore of the first plurality of pores; wherein the first selected pore ofthe first plurality of pores is different from the second selected poreof the first plurality of pores; wherein a first leg of the secondletter U shape is directly attached to the first conductive layer of afirst selected pore of the second plurality of pores; wherein a secondleg of the second letter U shape is directly attached to the firstconductive layer of a second selected pore of the second plurality ofpores; and wherein the first selected pore of the second plurality ofpores is different from the second selected pore of the second pluralityof pores.
 6. The porous two-wafer battery of claim 1, wherein the firstplurality of pores are symmetric with respect to a center of the firstwafer; and wherein the second plurality of pores are symmetric withrespect to a center of the second wafer.
 7. The porous two-wafer batteryof claim 6, wherein a centerline of the first wafer is aligned with acenterline of the second wafer.
 8. The porous two-wafer battery of claim6, wherein the first passivation layer directly contacts the secondpassivation layer.
 9. The porous two-wafer battery of claim 8, wherein acenterline of the first wafer offsets from a centerline of the secondwafer by a range from ten percent of a width of a selected pore of thefirst plurality of pores to fifty percent of the width of the selectedpore of the first plurality of pores.
 10. The porous two-wafer batteryof claim 1, wherein a first adhesion promotion layer is between thefirst conductive layer and the respective side wall of each of the firstplurality of pores; and wherein a second adhesion promotion layer isbetween the second conductive layer and the respective side wall of eachof the second plurality of pores.
 11. The porous two-wafer battery ofclaim 1, wherein the first wafer serves as an anode and the second waferserves as a cathode.
 12. The porous two-wafer battery of claim 1,wherein the first conductive layer and the second conductive layer aremade of a material selected from the group consisting of titaniumnitride, silicates, silicon carbide, copper, and nickel.
 13. The poroustwo-wafer battery of claim 1, wherein the first passivation layer andthe second passivation layer are made of a material selected from thegroup consisting of Ta2O5, HfO2, and SiN.
 14. The porous two-waferbattery of claim 1, wherein the first substrate further comprises afirst P+ doped region; and wherein the second substrate furthercomprises a second P+ doped region.